Integrated circuit (IC) devices typically include an IC chip that is housed in a plastic, ceramic or metal package. The IC chip typically includes a circuit fabricated by lithographically patterning conductive and insulating materials on a thin wafer of semiconductor material (e.g., silicon) using known fabrication techniques (e.g., CMOS). The package supports and protects the IC chip and provides electrical connections between the circuit and an external circuit or system.
Programmable Logic Devices (PLDs) are IC devices that are user configurable, and capable of implementing digital logic operations. There are several types of PLDs, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). CPLDs typically include several function blocks that are based on the well-known programmable logic array (PLA) architecture, and include a central interconnect matrix to transmit signals between the function blocks. Signals are transmitted into and out of the interconnect matrix through input/output blocks (IOBs). The input/output function of the IOBs, the logic performed by the function blocks and the signal paths implemented by the interconnect matrix are all controlled by configuration data stored in configuration memory of the CPLD. FPGAs include configurable logic blocks (CLBs) arranged in rows and columns, IOBs surrounding the CLBs, and programmable interconnect lines that extend between the rows and columns of CLBs. Each CLB includes look-up tables and other configurable circuitry that is programmable to implement a portion of a larger logic function. Similar to CPLDs, the CLBs, IOBs and interconnect lines of FPGAs are controlled by configuration data stored in a configuration memory of the FPGA.
Modern PLDs are highly complex, and often include more than one hundred Input/Output (I/O) structures (i.e., I/O (circuit) blocks and associated bonding pads connected to the I/O blocks) that access the programmable logic circuitry therein. To support the large number of I/O structures, PLDs are typically mounted in a package including multiple external contacts (e.g., pins, solder balls/bumps, or wire leads). Several package types are used to house PLD chips, including ball grid arrays (BGAs), pin grid arrays (PGAs), plastic leaded chip carriers, and plastic quad flat packs. The package type selected by an IC manufacturer for a particular IC chip is typically determined by the size/complexity of the IC chip (i.e., the number of input/output terminals), and also in accordance with a customer's requirements.
FIGS. 1 and 2 show bottom and side sectional views, respectively, of a typical BGA IC 100 including an IC chip 110 mounted on an upper surface 122 of a package substrate 120. Electrical connections between bonding pads 115 of IC chip 110 and contact pads 125 formed on upper surface 122 of substrate 120 are provided by bond wires 130. A plurality (sixty-four shown) of solder balls (sometimes referred to as solder bumps) 126 extend from a lower surface 127 of substrate 120 which are electrically connected to the conductive lines (not shown) and conductive vias 128 that are provided on substrate 120. Electrical signals travel between each solder ball 126 and one bonding pad 115 of IC chip 110 along an associated conductive line/via 128 and bond wire 124. For example, a test signal applied to solder ball 126-A is transmitted on conductive via 128A to contact pad 125A, and from contact pad 125A along bond wire 130A to bonding pad 115 of substrate 110. A cover 129, such as a cap or “glob top”, is placed or formed over IC chip 110 and bond wires 130 for protection.
IC manufacturers typically use IC testing systems to test their packaged IC devices before shipping to customers. IC testing systems typically include a device tester, a device handler and an interface apparatus. A device tester is an expensive piece of computing equipment that transmits test signals to the IC device under test via tester probes and the interface apparatus. The interface apparatus transmits signals between the leads of an IC device under test and the device tester. A device handler is an expensive precise robot for automatically moving IC devices from a storage area to the interface apparatus and back to the storage area. Such testing systems are well known.
FIGS. 3(A) and 3(B) show side and top views of a conventional interface apparatus 200 that is disclosed in U.S. Pat. No. 5,955,888.
Interface apparatus 200 includes a printed circuit board (PCB) 210 having mounted thereon a plurality of contact members (i.e., pogo pins) 220, a contactor body 240 mounted on PCB 210, and a nesting member 270 that is mounted over contactor body 240. PCB 210 includes connection structures (not shown) for receiving test signals from a device tester, and conductive lines (also not shown) for transmitting signals between the connection structures and pogo pins 220. Contactor body 240 includes four walls that are formed into a generally square or rectangular frame through which pogo pins 220 extend. A non-conductive plate 250 is mounted on an upper surface of contactor body 240 for aligning pogo pins 220 such that a tip 224 of each pogo pin 220 is aligned with a corresponding through-hole 276 formed in nesting member 270. Nesting member 270 is slidably mounted on shoulder bolts 245 that extend upward from contactor body 240, and is biased away from contactor body 240 by coil springs 260. Mounted on an upper surface 272 of nesting member 270 is a fixed (permanently attached) series alignment structures 280 that define an IC receiving (test) area 275, which includes through-holes 276.
Referring to FIG. 3(B), during a test procedure a BGA IC 100 is lowered into IC receiving area 275 of nesting member 270 by a device handler (not shown). Alignment structures 280 are formed with slanted walls 282 that facilitate “rough” alignment by causing BGA IC 100 to slide into IC receiving area 275. Subsequently, each solder ball 126 becomes engaged with an associated through-hole 276, which are chamfered to provide “fine” alignment of BGA IC 100 relative to pogo pins 220. BGA IC 100 and nesting member 270 are then pressed downward (as indicated by the arrow) to compress springs 260 until tips 224 of pogo pins 220 contact solder balls 126, thereby providing electrical connections between a testing device (not shown) connected to pogo pins 220 and IC device 100 for the testing procedure.
As FPGAs increase in size and performance, I/O resources become the main bottleneck to FPGA performance. Although the effective area of a chip grows as the square of the feature size, the perimeter I/Os grow only linearly. State of the art designs require higher performance I/O structures in order to compensate for this declining pin-to-gate ratio. In response to this increasing demand on I/O resources, Xilinx Inc. of San Jose, Calif. has developed high-speed I/O structures called Rocket I/O™ multi-gigabit transceivers (MGTs) that enable order-of-magnitude increases in I/O performance. The Rocket I/O MGTs double the total I/O bandwidth of the Xilinx Virtex-II Pro™ family of FPGA devices using only a few percent of the pins. With up to sixteen MGTs per device (the remaining I/O structures of the device being of a conventional general-purpose type), the Virtex-II Pro achieves an additional 100 gigabits per second of I/O bandwidth in the larger devices over FPGA devices utilizing only general-purpose I/O structures. Rocket I/O MGTs enable multiple gigabit I/O standards and maximize performance for FPGA-to-FPGA communications. Even though Rocket I/O MGTs dramatically increase performance for demanding applications, they are easy enough to use for simple FPGA-to-FPGA communications with special soft macros. The interface has been simplified to the extent that no external resistive termination is required with the Rocket I/O MGTs. The transceivers can be internally configured to match 50 ohm or 75 ohm transmission lines.
FPGAs (and other ICs) that include both general-purpose, relatively low-speed I/O structures and the new high-speed I/O structures (such as the Rocket I/O MGTs described above) present several challenges during device testing. One such problem is that conventional interface apparatus, such as interface apparatus 200 (described above) are typically built with contact members (e.g., pogo pins 220; see FIG. 3(A)) that are selected to support the relatively low-speed transmissions associated with the general-purpose I/O structures. Specifically, these contact members have impedances that are too high to support the high-speed communications associated with the high-speed I/O structures. One approach to correct this problem is to replace the sixteen contact members used to transmit signals to the high-speed I/O structures with low impedance, high-speed contact members. However, this mismatched arrangement (i.e., using some low-speed contact members and some high-speed contact members) creates new problems because high-speed contact members are typically shorter and have a lower spring constant that low-speed contact members. That is, the tips of the shorter, high-speed contact members would be further from the solder balls than the tips of the longer, low-speed contact members, thereby possibly preventing suitable contact during test procedures and impeding reliable testing of the IC device. Another approach that avoids the mismatch problem described above would be to replace all of the low-speed contact members with high-speed contact members. However, high-speed contact members are typically much more expensive than low-speed contact members, so the overall cost of an interface apparatus using only high-speed contact members would be undesirably high.
What is needed is a low-cost interface apparatus for testing ICs having both low-speed and high-speed I/O structures that avoids the problems described above.